Computer Science Canada

Makefile question
Author:  Geminias [ Wed Feb 13, 2008 8:34 pm ]
Post subject:  Makefile question
I know the basics, but I don't know exactly what is going on here:

code:

all: roll run

clean:
        rm -f *~ *.o roll test test.cpp

CXXTEST = ../..
CCFLAGS = -I. -I$(CXXTEST)

roll: roll.o Dice.o real_stdlib.o
        g++ -o $@ $^

run: test
        ./roll

test: test.o Dice.o mock_stdlib.o
        g++ -o $@ $^

.cpp.o:
        g++ -c -o $@ $(CCFLAGS) $<

test.cpp: TestDice.h
        $(CXXTEST)/cxxtestgen.pl -o $@ --error-printer $<


in particular, what are the $@? is that the same as bash script for all arguments? $<? $<?

How does it know to build test.cpp before test?
Author:  OneOffDriveByPoster [ Wed Feb 13, 2008 9:13 pm ]
Post subject:  Re: Makefile question
Geminias @ Wed Feb 13, 2008 8:34 pm wrote:
in particular, what are the $@? is that the same as bash script for all arguments? $<? $<?

How does it know to build .cpp before ?
http://www.tlug.org.za/old/csslug/writing_makefiles.html#makefile_builtinvars and the .cpp.o tells 'make' how to make .o files from .cpp files.
Author:  Geminias [ Wed Feb 13, 2008 9:59 pm ]
Post subject:  RE:Makefile question
Great thanks. One other question, say you have multiple programs that you want to be able to build seperately and also together, would you use makefiles for this or a script?

I've basically got directories P1 P2 P3. Each with its own make file. To make Program 1 it would be P1/Makefile. Program 2: P2/Makefile. etc...

Is it adviseable to try something like this for a makefile in the top directory like:

code:

#
#make file to build all 3 programs
#
all: build-P1 build-P2 build-P3

build-P1:
           make P1/Makefile

etc...
Author:  OneOffDriveByPoster [ Wed Feb 13, 2008 10:11 pm ]
Post subject:  Re: RE:Makefile question
Geminias @ Wed Feb 13, 2008 9:59 pm wrote:
I've basically got directories P1 P2 P3. Each with its own make file. To make Program 1 it would be P1/Makefile. Program 2: P2/Makefile. etc...
In my experience, a Makefile is appropriate at the top-level. Your structure looks okay; however, the normal way is to use
code:
        $(MAKE) -C P1
Author:  Geminias [ Thu Feb 14, 2008 9:59 am ]
Post subject:  RE:Makefile question
Alright great.

Does anyone know a better way to solve this?

code:

# Utils makefile
#
#
all: utils.o test.cpp buildtest runtest

CC=g++

SRCDIR=src
SOURCES=utils.cc
HEADERS=utils.h
TESTDIR=testing
TESTFILE=utils_test.h
TESTCPP=utils_test.cpp
OUTPUT=utils.o
OUT_EXEC=none


$(OUTPUT): $(SOURCES) $(HEADERS)
        $(CC) -c $(SRCDIR)/$(SOURCES) -o $(OUTPUT)

buildtest: $(OUTPUT) $(TESTCPP)
        $(CC) -o testsuite $^

utils.cc: #ISSUE# WHY MUST I DO THIS?
utils.h:  #ISSUE# IF I DONT PUT THESE HERE I GET THIS ERROR MSG:

#ERROR#make: *** No rule to make target `utils.h', ##needed by `utils.o'.  Stop.



$(TESTCPP): $(TESTDIR)/$(TESTFILE)
        cxxtestgen.pl -o $(TESTCPP) --error-printer $(TESTDIR)/$(TESTFILE)


runtest:
        ./testsuite

clean:
        rm *.o
Author:  OneOffDriveByPoster [ Thu Feb 14, 2008 2:55 pm ]
Post subject:  Re: RE:Makefile question
Please provide a file listing in the future.
Your problem is that your source files being referenced as dependencies are not in the same directory as your Makefile. Provide the path to the source files (not just the filename).
Author:  Geminias [ Thu Feb 14, 2008 3:25 pm ]
Post subject:  RE:Makefile question
Righto... Thanks again.

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